Heat sink layout designs for advanced finfet integrated circuits

ABSTRACT

A method of making a semiconductor device includes forming an active device region in a substrate. The method further includes forming a first transistor in the active device region, the first transistor including a first channel region a first source region and a first drain region. The method further includes forming a guard ring region outside the active device region. The method further includes forming a second transistor in the guard ring region, the second transistor comprising a second channel region a second source region and a second drain region. The second channel region includes a semiconductor material having a higher thermal conductivity than a semiconductor material of the first channel region.

PRIORITY CLAIM

This application is a continuation of U.S. application Ser. No.17/172,714, filed Feb. 10, 2021, which is a continuation of U.S.application Ser. No. 16/425,874, filed on May 29, 2019, now U.S. Pat.No. 10,923,572, issued Feb. 16, 2021, which claims the priority of U.S.Provisional Application No. 62/738,861, filed Sep. 28, 2018, which arehereby incorporated by reference in their entireties.

BACKGROUND

Miniaturizing integrated circuits (ICs) has resulted in smaller deviceswhich consume less power, yet provide more functionality at higherspeeds than before. The miniaturization process has also resulted invarious developments in IC designs and/or manufacturing processes tohelp to ensure device reliability and intended device performance.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more embodiments are illustrated by way of example, and not bylimitation, in the figures of the accompanying drawings, whereinelements having the same reference numeral designations represent likeelements throughout. It is emphasized that, in accordance with standardpractice in the industry various features may not be drawn to scale andare used for illustration purposes only. In fact, the dimensions of thevarious features in the drawings may be arbitrarily increased or reducedfor clarity of discussion.

FIG. 1A is a plan view of a layout of a semiconductor device, inaccordance with some embodiments.

FIG. 1B is a cross-sectional view of a semiconductor device manufacturedaccording to the layout of FIG. 1A and taken along line B-B′ in FIG. 1A,in accordance with some embodiments.

FIG. 1C is a cross-sectional view a semiconductor device manufacturedaccording to the layout of FIG. 1A and taken along line C-C′ in FIG. 1A,in accordance with some embodiments.

FIG. 2A is a plan view of a layout of a semiconductor device, inaccordance with some embodiments.

FIG. 2B is a cross-sectional view of a semiconductor device manufacturedaccording to the layout of FIG. 2A and taken along line B-B′ in FIG. 2A,in accordance with some embodiments.

FIG. 2C is a cross-sectional view a semiconductor device manufacturedaccording to the layout of FIG. 2A and taken along line C-C′ in FIG. 2A,in accordance with some embodiments.

FIG. 3 is a plan view of a layout of a semiconductor device, inaccordance with some embodiments.

FIG. 4 is a plan view of a layout of a semiconductor device, inaccordance with some embodiments.

FIG. 5 is a plan view of a layout of a semiconductor device, inaccordance with some embodiments.

FIG. 6 is a plan view of a layout of a semiconductor device, inaccordance with some embodiments.

FIG. 7 is a schematic diagram of an analog circuit, in accordance withsome embodiments.

FIG. 8A is a plan view of a layout of an analog circuit, in accordancewith some embodiments.

FIG. 8B is a cross-section view of a semiconductor device manufacturedaccording to the layout of FIG. 8A and taken along line B-B′ in FIG. 8A.

FIG. 9 is a schematic diagram of a system for designing a layout of asemiconductor device, in accordance with some embodiments.

FIG. 10 is a block diagram of a manufacturing system for making asemiconductor device, in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components, values, operations, materials,arrangements, or the like, are described below to simplify the presentdisclosure. These are, of course, merely examples and are not intendedto be limiting. Other components, values, operations, materials,arrangements, or the like, are contemplated. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. System may be otherwise oriented (rotated 90 degrees or atother orientations) and the spatially relative descriptors used hereinmay likewise be interpreted accordingly.

Integrated circuits often increase in temperature during use, whichoften limits the performance and reliability of the integrated circuits.Self-heating effects in complementary metal oxide semiconductor (CMOS)logic transistors are becoming increasingly difficult to resolve as thedimension of the device is continuously scaled down. The higheroperating temperature in the chip potentially causes many problems, suchas variation in device performance, increase in off-state current, andreduction in device reliability. For example, self-heating increases thetemperatures of metal interconnects, which accelerates electromigration(EM) failure of the metal interconnects. Self-heating also has adverseimpacts on intrinsic device reliability mechanisms, such as biastemperature instability (BTI) and hot carrier injection (HCI).

A recent trend of introduction of new geometrically confined devicestructures like fin field effect transistors (FinFETs) and continuousincorporation of new materials having low thermal conductivities in thedevice active regions and metal contacts to boost device performancefurther exacerbates self-heating and hence device reliability concerns.

FinFETs, for example, are increasingly used in many logic and otherapplications and are integrated into various different types ofsemiconductor devices. FinFETs include semiconductor fins with highaspect ratios in which channel and source/drain regions for transistorsare formed. A gate is formed over and along the sides of a portion ofthe semiconductor fins. The use of fins increases surface areas of thechannel and source/drain regions, resulting in faster, more reliable andbetter-controlled transistors which consume less power in comparisonwith planar transistors. However, FinFET architectures result insignificant self-heating due to the higher device density and narrowerconductive path (small fin widths) compared to the planar metal oxidesemiconductor field effect transistor (MOSFET) devices.

Strained silicon germanium (SiGe) has recently been used as a highmobility channel material in FinFETs. However, SiGe has a lower thermalconductivity than Si. For example, the thermal conductivity of SiGe with50% of Ge is only about 10% of the thermal conductivity of pure Si. Thelow thermal conductivity of SiGe makes conduction cooling through thesubstrate less efficient, and increases the concerns associated withself-heating. Furthermore, as new technology uses cobalt (Co) with muchhigher electrical conductivity than copper as source/drain contacts,heat dissipation through upper interconnect metal layers inback-end-of-line (BEOL) is also impeded due to decreased thermalconductivity of cobalt compared to the copper or tungsten counterpart.

Therefore, self-heating has become a design concern for high performancecircuitry as technology scales to even smaller dimensions. Other FinFETlayout designs, however, do not sufficiently dissipate heat becauseother FinFET layout designs lack effective heat dissipation paths fordiverting heat into the substrate.

Embodiments of the present disclosure provide FinFET design layouts withimproved heat dissipation capability in comparison with otherapproaches. In some embodiments, the FinFET design layout includes guardring, dummy devices or resistors to help to dissipate heat generated byactive FinFETs to the substrate, thereby overcoming or reducing problemsassociated with self-heating resulting from low thermal transport ofchannel materials and contact metals in FinFET based integratedcircuits. In some embodiments, the layouts of the present disclosure areuseful for improving reliability of analog, mixed signal or radiofrequency (RF) circuits.

FIG. 1A is a plan view of a layout 100 of a semiconductor device, inaccordance with some embodiments.

Referring to FIG. 1A, layout 100 includes a plurality of semiconductorfins 110, 120 and a plurality of gate structures 130 usable forformation of a plurality FinFETs 140 a in an active device region 100 aand a plurality of FinFETs 140 b in a guard ring region 100 b adjacentto active device region 100 a. FinFETs 140 a in active device region 100a are capable of performing functions of an integrated circuit, however,FinFETs 140 b in guard ring region 100 b are not used for performingfunctions of the integrated circuit, rather FinFETs 140 b are employedto provide electromagnetic shielding between different portions of theintegrated circuit, so that devices in the integrated circuit maintainproper performance despite parasitic effect from neighboring devices. Inuse, FinFETs 140 a generate heat. Because no or negligible power isapplied to FinFETs 140 b in guard ring region 100 b, guard ring region100 b functions as a heat sink to remove the heat generated by FinFETs140 a. Guard ring region 100 b is thus employed not only to provideelectromagnetic shielding for FinFETs 140 a in active device region 100a, but also to help to dissipate heat generated by FinFETs 140 a.Dissipating the generated heat from active device region 100 a mitigateselectromigration degradation in BEOL interconnect metal layers, forexample.

Active device region 100 a includes at least one semiconductor fin 110,and guard ring region 100 b includes at least one semiconductor fin 120.Although a single semiconductor fin 110 in active device region 100 aand a single semiconductor fin 120 in guard ring region 100 b areillustrated, the scope of the present disclosure is not limited thereto,and any number of semiconductor fins 110 and 120 are contemplated inactive device region 100 a and guard ring region 100 b. Semiconductorfins 110, 120 extend along a first direction, e.g., the x direction andare isolated from each other by isolation structures 104. Adjacentsemiconductor fins 110 and 112 in corresponding active device region 100a and guard ring region 100 b are separated from each other by a spacingS1. A minimum spacing permitted by design rules for spacing S1 helps tomaximize heat dissipation rate. In some embodiments, the at least onesemiconductor fin 120 in guard ring region 100 b is of similar size andshape as the at least one semiconductor fin 110 in active device region100 a. In other embodiments, semiconductor fin 120 in guard ring region100 b is substantially larger or smaller than semiconductor fin 110 inactive device region 100 a.

Gate structures 130 extend along a second direction, e.g., the ydirection, across semiconductor fins 110, 120. In some embodiments, thesecond direction y is perpendicular to the first direction x. In someembodiments, gate structures 130 have a uniform pitch. A gate pitch p isdefined as the summation of the width of a single gate structure and thedistance between the single gate structure and an adjacent gatestructure. In some embodiments, gate structures 130 have pitchesdifferent from each other. When gate structures 130 have a constantpitch, greater control over the critical dimension of gate structures130 is achieved. Although eight gate structures are in FIG. 1A, thescope of the present disclosure is not limited thereto. In someembodiments, a single gate structure or a different number of gatestructures is used. Gate structures 130 include gate structures 130 athat cross over semiconductor fin 110 in active device region 100 a, andgate structures 130 b that cross over semiconductor fin 120 in guardring region 100 b.

Each FinFET 140 a in active device region 100 a includes a channelregion 112 in a portion of semiconductor fin 110 underlying acorresponding gate structure 130 a, and a source region 114 and a drainregion 116 in portions of semiconductor fin 110 on opposite sides of thecorresponding gate structure 130 a. Source region 114 and drain region116 surrounds channel region 112. Each FinFET 140 b in guard ring region100 b includes a channel region 122 in a portion of semiconductor fin120 underlying a corresponding gate structure 130 b, and a source region124 and a drain region 126 in portions of semiconductor fin 120 onopposite sides of the corresponding gate structure 130 b. Source region124 and drain region 126 surround channel region 122. Channel regions112, 122 are relatively lightly doped regions, while source regions 114,124 and drain regions 116, 126 are relatively heavily doped regions. Insome embodiments, channel regions 112 and 122 include dopants of a firstconductivity type, while source regions 114, 124 and drain regions 116,126 includes dopants of a second conductivity type opposite the firstconductivity type. In some embodiments, when the first conductivity typeis p-type, the second conductivity type is n-type, or vice versa. Insome embodiments, channel regions 112, 122 include n-type dopants, whilesource regions 114, 124 and drain regions 116, 126 include p-typedopants for formation of p-type FinFETs (pFinFETs). In some embodiments,channel regions 112, 122 include p-type dopants, while source regions114, 124 and drain regions 116, 126 include n-type dopants for formationof n-type FinFETs (nFinFETs).

Layout 100 further includes a gate cut layer 150 extending along thefirst direction. Gate cut layer 150 is usable to identify locationswhere gate structures 130 are removed for electrical disconnectionaccording to the integrated circuit design. Gate cut layer 150 in FIG.1A is between active device region 100 a and guard ring region 100 b toindicate that gate structures 130 a and 103 b are disconnected from oneanother. In the design and manufacturing process of layout 100 onphysical wafers, the presence of gate cut layer 150 indicates that gatestructures 130 are initially formed as long and continuous stripsextending through active device region 100 a and guard ring region 100b, and then etched (cut) into shorter pieces in subsequent processes toprovide gate structures 130 a, 130 b in respective active device region100 a and guard ring region 100 b.

Layout 100 further includes a channel block layer 160 over guard ringregion 100 b. Channel block layer 160 is placed in alignment withchannel regions 122 and is usable to indicate that a semiconductormaterial having a higher thermal conductivity than the semiconductormaterial provided channel regions 112 is used as a channel material inchannel regions 122. Channel regions 122 are thus provided with highheat dissipation capacity and are usable to remove heat from activedevice region 100 a to guard ring region 100 b. In some embodiments,channel block layer 160 is a SiGe block layer when SiGe is employed as achannel material for enhancing carrier mobility in FinFET 140 a. Thepresence of SiGe block layer indicates that SiGe is only present inchannel regions 112, but not in channel regions 122, and instead asemiconductor material with a higher thermal conductivity than SiGe isused as the channel material in FinFET 140 b to facilitate the heatdissipation to guard ring region 100 b. In some embodiments, whenchannel regions 112 of FinFETs 140 a in active device region 100 ainclude SiGe, channel regions 122 of FinFETs 140 b in guard ring region100 b include an intrinsic (non-doped) Si or a lightly doped Si. As usedherein, lightly doped means a doping concentration less than about1×10¹³ atoms/cm³. Because FinFETs 140 b in guard ring region 100 b areinactive devices, absence of SiGe in channel regions 122 of FinFETs 140b has no impact on circuit performance.

Channel block layer 160 is able to be generated using the availablecomputer-aided design (CAD) library, therefore introducing channel blocklayer 160 in layout 100 is completed without creating any new CAD layer.

Layout 100 further includes a plurality of source contact structures 172and a plurality of drain contact structures 174 a and 174 b. Sourcecontact structures 172 extend from active device region 100 a to guardring region 100 b. Each source contact structure 172 is over acorresponding source region 114 in active device region 100 a and acorresponding source region 124 in guard ring region 100 b, so as tocouple the corresponding source region 114 in active device region 100 ato the corresponding source region 124 in guard ring region 100 b. Eachsource contact structure 172 thus functions as a heat conductive layerand helps to remove the heat generated by FinFETs 140 a from sourceregions 114 of FinFETs 140 a to guard ring region 100 b. In someembodiments, each source contact structure 172 directly couples acorresponding source region 114 in active device region 100 a to acorresponding source region 124 in guard ring region 100 b. Draincontact structures include a first set of drain contact structures 174 aover drain regions 116 of FinFETs 140 a in active device region 100 a,and a second set of drain contact structures 174 b over drain regions126 of FinFETs 140 b in guard ring region 100 b. Drain contactstructures 174 a are configured to provide electrical connection to theunderlying drain regions 116 of FinFETs 140 a in active device region100 a, while drain contact structures 174 b are configured to provideelectrical connection to the underlying drain regions 126 of FinFETs 140b in guard ring region 100 b.

Layout 100 further includes a plurality of interconnect metal layers180. Each interconnect metal layer 180 contacts at least one via 182over a first portion of a corresponding source contact structure 172 inactive device region 100 a and at least one via 184 over a secondportion of the corresponding source contact structure 172 in guard ringregion 100 b, thereby additionally coupling a corresponding sourceregion 114 to guarding ring region 100 b by way of at least the at leastone via 182, the interconnect metal layer 180, and the at least one via184. Each interconnect metal layer 180 thus functions as a heatconductive layer to provide an additional heat dissipation path throughwhich the heat removed by a corresponding source contact structure 172is transferred to the upper interconnect metal layers (not shown) inBEOL by way of vias 182, 184 and interconnect metal layer 180. In someembodiments, each interconnect metal layer 180 is used in the integratedcircuit as an electrically coupled component configured to connect acorresponding source region 114 in active device region 100 a to one ormore other components of the integrated circuit.

In some embodiments, layout 100 is represented by a plurality of masksgenerated by one or more processors and/or stored in one or morenon-transitory computer-readable media. Other formats for representinglayout 100 are within the scope of various embodiments. Examples of anon-transitory computer readable recording medium include, but are notlimited to, external/removable and/or internal/built-in storage ormemory unit, e.g., one or more of an optical disk, such as a DVD, amagnetic disk, such as a hard disk, a semiconductor memory, such as aROM, a RAM, a memory card, and the like. For example, layout 100 ispresented by at least one first mask corresponding to semiconductor fins110, 120, at least one second mask corresponding to gate structures 130,at least one third mask corresponding to gate cut layer 150, at leastone fourth mask corresponding to channel block layer 160, at least onefifth mask corresponding to source contact structures 172 and draincontact structures 174 a, 174 b, and at least one sixth maskcorresponding to interconnect metal layers 180 and vias 182, 184.

FIGS. 1B and 1C are cross-sectional views of a semiconductor device 100′manufactured according to the layout 100 depicted in FIG. 1A. Thecross-sectional view in FIG. 1B is taken along line B-B′ in FIG. 1A. Thecross-sectional view in FIG. 1C is taken along line C-C′ in FIG. 1A.Semiconductor device 100′ is a non-limiting example for facilitating theillustration of the present disclosure. The configuration of thesemiconductor device 100′ is described herein with respect to both FIG.1B and FIG. 1C.

Referring to FIGS. 1B and 1C, semiconductor device 100′ includes asubstrate 102 and isolation structures 104, semiconductor fins 110, 120,and gate structures 103 a, 103 b over substrate 102. In someembodiments, substrate 102 is a silicon substrate, or a substrate formedof other suitable semiconductor materials. In some embodiments,substrate 102 is doped with n-type or p-type dopants. Isolationstructures 104 electrically isolate various components of semiconductordevice 100′ from one another. In some embodiments, isolation structures104 include a dielectric material such as silicon dioxide, siliconnitride, silicon oxynitride, or any other suitable insulating material.Semiconductor fins 110 and 120 extend above the top surfaces ofisolation structures 104 and are electrically isolated from each otherby isolation structures 104. At least one semiconductor fin 110 is inactive device region 100 a of substrate 102. Gate structures 130 a crosssemiconductor fin 110 to define FinFETs 140 a in active device region100 a of substrate 102. At least one semiconductor fin 120 is in guardring region 100 b of substrate 102. Gate structures 130 b crosssemiconductor fin 120 to define FinFETs 140 b in guard ring region 100 bof substrate 102. FinFETs 140 a and 140 b have similar structures andwill be described collectively below.

Each FinFET 140 a in active device region 100 a includes a gatestructure 130 a across a channel region 112 of semiconductor fin 110,and a source region 114 and a drain region 116 in portions ofsemiconductor fin 110 on opposite sides of the gate structure 130 a.Each FinFET 140 b in guard ring region 100 b includes a gate structure130 b across a channel region 122 of semiconductor fin 120, and a sourceregion 124 and a drain region 126 in portions of semiconductor fin 120on opposite sides of the gate structure 130 b. In some embodiments,FinFETs 140 a, 140 b are nFinFETs, channel regions 112, 122 thus includep-type dopants such as boron, and source regions 114, 124 and drainregions 116, 126 include n-type dopants such as phosphorous or arsenic.To facilitate heat dissipation through substrate 102, respective channelregions 122 in guard ring regions 110 b are provided with asemiconductor material having a thermal conductivity greater than athermal conductivity of a semiconductor material that provide respectivechannel regions 112 in active device regions 110 a. Channel regions 122thus act as heat sinks to dissipate the heat generated by FinFETs 140 ato substrate 102. In some embodiments, when channel regions 112 ofFinFET 140 a in active device region 100 a include SiGe for increasingelectron mobility of nFinFETs, channel regions 122 of FinFETs 140 b inguard ring region 100 b include Si to facilitate heat dissipationthrough substrate 102.

In some embodiments, each gate structure 130 a, 130 b contactssemiconductor fin 110, 120 on top surface and sidewalls thereof. In someembodiments, each gate structure 130 a, 130 b only contacts thesidewalls of semiconductor fin 110, 120 (not shown). Each gate structure130 a, 130 b includes a gate dielectric layer 132 and a gate electrodelayer 134. Example materials of gate dielectric layers 132 include, butare not limited to, a high-k dielectric layer, an interfacial layer,and/or combinations thereof. Example materials for the high-k dielectriclayer include, but are not limited to, silicon nitride, siliconoxynitride, hafnium oxide (HfO₂), hafnium silicon oxide (HfSiO), hafniumsilicon oxynitride (HfSiON), hafnium tantalum oxide (HMO), hafniumtitanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), metal oxides,metal nitrides, metal silicates, transition metal-oxides, transitionmetal-nitrides, transition metal-silicates, oxynitrides of metals, metalaluminates, zirconium silicate, zirconium aluminate, zirconium oxide,titanium oxide, aluminum oxide, hafnium dioxide-alumina (HfO₂—Al₂O₃)alloy, suitable high-k dielectric materials, and/or combinationsthereof. In some embodiments, gate dielectric layer 132 includesmulti-layer structure of, for example, SiO₂ with a high-k dielectric, orSiON with a high-k dielectric. In some embodiments, gate electrodelayers 134 include a doped polycrystalline silicon (polysilicon).Alternatively, gate electrode layer 134 includes a metal such asaluminum, copper, tungsten, titanium, thallium, TiN, TaN, NiSi, CoSi,other suitable conductive materials, or combinations thereof.

Semiconductor device 100′ further includes strained relaxed buffer (SRB)layers 118, 128. In the example configuration in FIGS. 1B and 1C,semiconductor device 100′ includes an SRB layer 118 located betweensemiconductor fin 110 and substrate 102 in active device region 100 aand an SRB layer 128 located between semiconductor fin 120 and substrate102 in guard ring region 100 b. SRB layers 118 and 128 are surrounded byisolation structures 104. In some embodiments, SRB layer 118 and SRBlayer 128 are merged at the bottom thereof to form a common SRB layer108 for semiconductor fin 110 and semiconductor fin 120. In someembodiments, SRB layer 118 and SRB layer 128 are separated at the bottom(not shown). SRB layers 118 include a material capable of increasingstress of channel regions 112 of FinFETs 140 a. In some embodiments,when channel regions 112 of FinFETs 140 a include SiGe having about 75%Si and 25% Ge for nFinFETs, SRB layers 118 include SiGe having about 50%of Si and 50% of Ge. SRB layer 118 provides a tensile stress to channelregions 112, thereby increasing the electron mobility in channel regions112. As a result, the performance of FinFET 140 a is enhanced. SRBlayers 128 include a same material as SRB layer 118.

Semiconductor device 100′ further includes contact structures to provideelectrical connections to FinFETs 140 a and FinFETs 140 b. The contactstructures includes source contact structures 172 for coupling sourceregions 114 of FinFETs 140 a in active device region 100 a to sourceregions 124 of FinFETs 140 b in guard ring region, drain contactstructures 174 a (FIG. 1A) overlying drain regions 116 (FIG. 1A) ofFinFETs 140 a in active device region 100 a, and drain contactstructures 174 b (FIG. 1A) overlying drain regions 126 (FIG. 1A) ofFinFETs 140 b in guard ring region 100 b. Source contact structures 172and drain contact structures 174 a, 174 b include a metal such as, forexample, cobalt, copper, or tungsten.

Semiconductor device 100′ further includes interconnect metal layers 180to electrically couple source contact structures 172 with one or moreother components of semiconductor device 100′. Each interconnect metallayer 180 contacts at least one via 182 over a first portion of acorresponding source contact structure 172 in active device region 100 aand at least one via 184 over a second portion of the correspondingsource contact structure 172 in guard ring region 100 b to provide anadditional heat dissipation path for FinFETs 140 a through which theheat generated by FinFETs 140 a is transferred to upper interconnectmetal layers (not shown) of BEOL. Interconnect metal layers 180 and vias182, 184 include, for example, aluminum, copper, tungsten, or alloysthereof.

The dashed arrows in FIGS. 1B and 1C show the heat dissipation paths insemiconductor device 100′. By utilizing a semiconductor material withhigh thermal conductivity as a channel material in channel regions 122of FinFETs 140 b in guard ring region 100 b, heat generated by FinFETs140 a is able to be removed out of the structure through substrate 102by way of channel regions 122 in guard ring region 100 b as indicated byarrow 193 (FIG. 1B). In addition, some of the heat generated by FinFET140 a is dissipated from source regions 114 of FinFETs 140 a to guardring region 100 b and then to substrate 102 by way of source contactstructures 172 as indicated by arrow 195. Furthermore, some of the heatremoved by source contact structures 172 is also able to be dissipatedout of the structure through interconnect metal layers 180 above sourcecontact structures 172 and further through upper interconnect metallayers (not shown) of BEOL as indicated by arrow 197.

FIG. 2A is a plan view of a layout 200 of a semiconductor device, inaccordance with some embodiments. In comparison with layout 100 of FIG.1A, in layout 200, an epitaxial block layer 260 replaces channel blocklayer 160 in guard ring region 100 b for creating structures that allowsbetter dissipating the heat. In some embodiments, in layout 200, gatestructures 130 b are removed from guard ring region 100 b to furtherfacilitate the heat dissipation. In some embodiments, gate structures130 b remain in guard ring region 100 b (not shown).

Components in layout 200 that are the same or similar to those in FIGS.1A-1C are given the same references numbers, and detailed descriptionthereof is thus omitted.

Referring to FIG. 2A, epitaxial block layer 260 is placed in guard ringregion 100 b. Epitaxial block layer 260 is usable to indicate that allthe materials having low thermal conductivities used in the epitaxialregions including channel regions 112, source regions 114 and drainregions 116 of FinFETs 140 a as well as SRB layer 118 in active deviceregion 110 a are blocked in guard ring region 100 b. Therefore, onlysemiconductor materials having high thermal conductivities are utilizedin guard ring region 100 b. In some embodiments, guard ring region 100 bincludes a semiconductor material having a thermal conductivity greaterthan 100 W/mk. Depending on design rules, in some embodiments, epitaxialblock layer 260 is provided as a continuous layer to cover an entiretyof guard ring region 100 b (not shown), and in some embodiments,epitaxial block layer 260 is provided as a plurality of non-continuoussegments such that only portions of guard ring region 100 b where highthermal conductivity semiconductor material are desirable are covered byepitaxial block layer 260 (FIG. 2A). Similar to channel block layer 160in layout 100 of FIG. 1A, epitaxial block layer 260 in layout 200 isable to be generated using the available computer-aided design (CAD)library, therefore introducing epitaxial block layer 260 in layout 200is completed without creating any new CAD layer.

In some embodiments, layout 200 is represented by a plurality of masksgenerated by one or more processors and/or stored in one or morenon-transitory computer-readable media. Other formats for representinglayout 200 are within the scope of various embodiments. Examples of anon-transitory computer readable recording medium include, but are notlimited to, external/removable and/or internal/built-in storage ormemory unit, e.g., one or more of an optical disk, such as a DVD, amagnetic disk, such as a hard disk, a semiconductor memory, such as aROM, a RAM, a memory card, and the like. For example, layout 200 ispresented by at least one first mask corresponding to semiconductor fins110, 120, at least one second mask corresponding to gate structures 130a, at least one third mask corresponding to epitaxial block layer 260,at least one fourth mask corresponding to source contact structures 172and drain contact structures 174 a, 174 b, and at least one fifth maskcorresponding to interconnect metal layers 180 and vias 182, 184.

FIGS. 2B and 2C are cross-sectional views of a semiconductor device 200′manufactured according to the layout 200 of FIG. 2A. The cross-sectionalview in FIG. 2B is taken along line B-B′ in FIG. 2A. The cross-sectionalview in FIG. 2C is taken along line C-C′ in FIG. 2A. The configurationof the semiconductor device 200′ is described herein with respect toboth FIG. 2B and FIG. 2C. Components in semiconductor device 200′ thatare the same or similar to those in FIGS. 1A-1C are given the samereferences numbers, and detailed description thereof is thus omitted.

Referring to FIGS. 2B and 2C, in comparison with semiconductor device100′ of FIGS. 1B and 1C, in semiconductor device 200′, SRB layer 128 isnot formed in guard ring region 100 b such that semiconductor fin 120 inguard ring region 100 b is in direct contact with substrate 102 toenable a direct heat dissipation from semiconductor fin 120 to theunderlying substrate 102. In addition, an entire semiconductor fin 120in guard ring region 100 b is provided to comprise a semiconductormaterial having a higher thermal conductivity than semiconductormaterials that provide respective channel regions 112, source regions114 and drain regions 116 of FinFETs 140 a in active device region 100 aso as to provide an increased heat dissipating surface area. Forexample, in active device region 100 a, when channel regions 112 includestrained Si, and source regions 114 and drain regions 116 includen-doped SiGe for formation of nFinFETs 140 a, or when channel regions112 include strained SiGe, and source regions 114 and drain regions 116include p-doped SiGe for formation of pFinFETs 140 a, SiGe is not usedin guard ring region 100 b, and semiconductor fin 120 in guard ringregion 100 b comprises solely Si which has a higher thermal conductivitythan SiGe.

Furthermore, gate structures 130 b are also removed from guard ringregion 100 b. The removal of gate structures 130 b removes dielectricmaterials employed in gate structures 130 b that have relatively poorconductivities from guard ring region 100 b so as to further facilitatethe heat dissipation through substrate 102.

Eliminating both gate structures 130 a and epitaxial semiconductormaterials with low thermal conductivities in guard ring region 100 bresults in more efficient heat removal through substrate 102.

Similar to semiconductor device 100′ of FIGS. 1B and 1C, the heatgenerated by FinFETs 140 a in active device region 100 a is able to bedissipated through substrate 102 as indicated by arrow 193, throughsource contact structures 172 as indicated by arrow 195, and throughinterconnect metal layers 180 as indicated by arrow 197.

FIG. 3 is a plan view of a layout 300 of a semiconductor device, inaccordance with some embodiments. In comparison with layout 100 of FIG.1A, in layout 300, FinFETs 140 b in guard ring region 100 b areconfigured to have a channel length greater than a channel length ofFinFETs 140 a in active device region 100 a. Components in FIG. 3 thatare the same or similar to those in FIGS. 1A-1C are given the samereferences numbers, and detailed description thereof is thus omitted.

Referring to FIG. 3 , layout 300 includes FinFETs 140 a in active deviceregion 100 a and FinFETs 140 b in guard ring region 100 b. Each FinFET140 a includes a gate structure 130 a across a channel region 112 of asemiconductor fin 110. Each FinFET 140 b includes a gate structure 130 bacross a channel region 122 of a semiconductor fin 120. A channel lengthof a FinFET is defined by the width of a gate structure. In layout 300,each gate structure 130 a in active device region 110 a has a width W1measurable along the x direction, and each gate structure 130 b in guardring region 100 b has a width W2 measurable along the x direction. Thewidth W2 is set to be greater than the width W1 so as to provide agreater channel length for FinFET 140 b in guard ring region 100 b. Thegreater channel length of FinFETs 140 b in guard ring region 100 bincreases heat dissipation surface area, thereby allowing more heat tobe dissipated through underlying substrate. As a result, theself-heating effect of the resulting integrated circuit is reduced.

Unlike layout 100 in which a single source contact structure 172 is usedto couple both source region 114 in active device region 100 a andsource region 124 in guard ring region 100 b, in layout 300 sourcecontact structures 172 a are formed to contact respective source regions114 of FinFETs 140 a in active device region 100 a and source contactstructures 172 b are formed to contact respective source region 124 inguard ring region 100 b. Source contact structures 172 a provideelectrical connection to source regions 114, while source contactstructures 172 b provide electrical connection to source regions 124.Because no single source contact structure that couples both sourceregion 114 and source region 124 is available in layout 300, heatdissipation in layout 300 is mainly through the substrate over whichFinFETs 140 a, 140 b are formed.

In some embodiments, layout 300 is represented by a plurality of masksgenerated by one or more processors and/or stored in one or morenon-transitory computer-readable media. Other formats for representinglayout 300 are within the scope of various embodiments. Examples of anon-transitory computer readable recording medium include, but are notlimited to, external/removable and/or internal/built-in storage ormemory unit, e.g., one or more of an optical disk, such as a DVD, amagnetic disk, such as a hard disk, a semiconductor memory, such as aROM, a RAM, a memory card, and the like. For example, layout 300 ispresented by at least one first mask corresponding to semiconductor fins110, 120, at least one second mask corresponding to gate structures 130a, 130 b, at least one third mask corresponding to channel block layer160, at least one fourth mask corresponding to source contact structures172 a, 172 b and drain contact structures 174 a, 174 b, and at least onefifth mask corresponding to interconnect metal layers 180 and vias 182,184.

Layout 300 uses a channel block layer 160 in guard ring region 100 b,one of ordinary skill would understand that using epitaxial block layer260 of FIG. 2A in guard ring region 100 b is contemplated and within thescope of the present disclosure.

FIG. 4 is a plan view of a layout 400 of a semiconductor device, inaccordance with some embodiments. In comparison with layout 100 of FIG.1A, in layout 400, gate structures 130 b in guard ring region 100 b areconfigured to have a gate pitch P2 greater than a gate pitch P1 of gatestructures 130 a in active device region 100 a. Components in FIG. 4that are the same or similar to those in FIGS. 1A-1C are given the samereferences numbers, and detailed description thereof is thus omitted.

Referring to FIG. 4 , layout 400 includes FinFETs 140 a in active deviceregion 100 a and FinFETs 140 b in guard ring region 100 b. Each FinFET140 a includes a gate structure 130 a across a channel region 112 of asemiconductor fin 110. Each FinFET 140 b includes a gate structure 130 bacross a channel region 122 of a semiconductor fin 120. In layout 400,gate structures 130 a in active device region 100 a have a pitch P1measurable along the x direction, and gate structures 130 b in guardring region 100 b have a pitch P2 measurable along the x direction. Thegate pitch P2 is set to be greater than the gate pitch P1. The greatergate pitch for gate structures 130 b in guard ring region 100 b helps toreduce the self-heating effect of the resulting integrated circuit dueto larger area for heat dissipation. In some embodiments and as shown inFIG. 4 , gate structures 130 b have a same width as the gate structures130 a, while source regions 124 have a greater width than source region114, and drain regions 126 have a greater width than drain regions 116.

Layout 400 further includes source contact structures 172 a contactingrespective source regions 114 of FinFETs 140 a in active device region100 a and source contact structures 172 b contacting respective sourceregion 124 in guard ring region 100 b. Source contact structures 172 aprovide electrical connection to source regions 114, while sourcecontact structures 172 b provide electrical connection to source region124. Because no single source contact structure that couples both sourceregion 114 and source region 124 is available in layout 400, heatdissipation in layout 400 is mainly through the underlying substrate.

In some embodiments, layout 400 is represented by a plurality of masksgenerated by one or more processors and/or stored in one or morenon-transitory computer-readable media. Other formats for representinglayout 400 are within the scope of various embodiments. Examples of anon-transitory computer readable recording medium include, but are notlimited to, external/removable and/or internal/built-in storage ormemory unit, e.g., one or more of an optical disk, such as a DVD, amagnetic disk, such as a hard disk, a semiconductor memory, such as aROM, a RAM, a memory card, and the like. For example, layout 400 ispresented by at least one first mask corresponding to semiconductor fins110, 120, at least one second mask corresponding to gate structures 130a, 130 b, at least one third mask corresponding to channel block layer160, at least one fourth mask corresponding to source contact structures172 a, 172 b and drain contact structures 174 a, 174 b, and at least onefifth mask corresponding to interconnect metal layers 180 and vias 182,184.

Layout 400 uses a channel block layer 160 in guard ring region 100 b,one of ordinary skill would understand that using epitaxial block layer260 of FIG. 2A in guard ring region 100 b is contemplated and within thescope of the present disclosure.

FIG. 5 is a plan view of a layout 500 of a semiconductor device, inaccordance with some embodiments. In comparison with layout 100 of FIG.1A, in layout 500, a native, or NT_N layer 560 replaces channel blocklayer 160 in guard ring region 100 b. Components in FIG. 5 that are thesame or similar to those in FIGS. 1A-1C are given the same referencesnumbers, and detailed description thereof is thus omitted.

Referring to FIG. 5 , NT_N layer 560 is in alignment with channelregions 122 of FinFETs 140 b. NT_N layer 560 is usable to define regionsdevoid of doping. In some embodiments, NT_N layer 560 is added in layout500 to indicate that channel regions 122 of FinFETs 140 b in guard ringregion 100 b are not doped with either p-type dopants or n-type dopants.In some embodiments, NT_N layer 560 is added in layout 500 to indicatethat channel regions 122 of FinFETs 140 b in guard ring region 100 bhave a lower doping concentration than the doping concentration ofchannel regions 112 of FinFET 140 a in active device region 100 a.Higher doping concentration has been known to reduce the thermalconductivity of Si due to the increased phonon boundary scattering.Thus, the reduction of the doping concentration in channel regions 122in guard ring region 100 b reduces the thermal resistance of channelmaterial, which helps to facilitate heat dissipation through theunderlying substrate.

Similar to channel block layer 160 in layout 100 of FIG. 1A, NT_N layer560 in layout 500 is able to be generated using the availablecomputer-aided design (CAD) library, therefore introducing NT_N layer560 in layout 500 is completed without creating any new CAD layer.

Layout 500 is able to dissipate generated heat out of the structure byway of underlying substrate, source contact structures 172 andinterconnect metal layers 180.

Though in layout 500, gate structures 130 b in guard ring region 100 bare illustrated as having the same gate width and the same gate spacingas gate structures 130 a in active device region 100 a, in someembodiments, gate structures 130 b with larger gate width and/or largergate spacing illustrated in FIGS. 3 and 4 in conjunction with the addingof NT_N layer 560 to further increase heat dissipation capabilities ofthe integrated circuit are contemplated.

In some embodiments, layout 500 is represented by a plurality of masksgenerated by one or more processors and/or stored in one or morenon-transitory computer-readable media. Other formats for representinglayout 500 are within the scope of various embodiments. Examples of anon-transitory computer readable recording medium include, but are notlimited to, external/removable and/or internal/built-in storage ormemory unit, e.g., one or more of an optical disk, such as a DVD, amagnetic disk, such as a hard disk, a semiconductor memory, such as aROM, a RAM, a memory card, and the like. For example, layout 500 ispresented by at least one first mask corresponding to semiconductor fins110, 120, at least one second mask corresponding to gate structures 130,at least one third mask corresponding to gate cut layer 150, at leastone fourth mask corresponding to NT_N layer 560, at least one fifth maskcorresponding to source contact structures 172 and drain contactstructures 174 a, 174 b, and at least one six mask corresponding tointerconnect metal layers 180 and vias 182, 184.

FIG. 6 is a plan view of a layout 600 of a semiconductor device, inaccordance with some embodiments. In comparison with layout 100 in FIG.1A, in layout 600 dummy FinFETs 140 c in a dummy device region 100 creplace FinFETs 140 b in guard ring region 100 b. Components in FIG. 6that are the same or similar to those in FIGS. 1A-1C are given the samereferences numbers, and detailed description thereof is thus omitted.

Referring to FIG. 6 , layout 600 includes FinFETs 140 a in active deviceregion 100 a and dummy FinFETs 140 c in a dummy device region 100 c thatis in a close proximity to active device region 100 a. As used herein, adummy structure is referred to as a structure which is utilized to mimica physical property of another structure and which is circuit inoperable(i.e., which is not part of a circuit current flow path) in the finalfabricated device. Dummy FinFETs 140 c thus are substantially identicalin configuration to FinFET 140 a in active device region 100 a, but arenot used to control current flow between source and drain regions basedon a gate voltage. Detailed description for components of dummy FinFETs140 c are therefore omitted. Because no current is flow through dummyFinFETs 140 c, dummy FinFETs 140 c help to remove heat from FinFETs 140a in active device region 110 a through the underlying substrate. Insome embodiments, dummy FinFETs 140 c are included in layout 600 notonly to dissipate heat, but also to mitigate the impact ofnon-idealities with respect to active FinFETs (i.e., FinFETs 140 a)occurred during fabrication, thereby making manufacturability of theresulted integrated circuit more efficient. A minimum spacing S1 allowedby design rules between active device region 100 a and dummy deviceregion 100 c is desirable to maximize heat dissipation rate.

In layout 600, channel block layer 160 is over dummy device region 100 cand is aligned with channel regions of dummy FinFETs 140 c. The presenceof channel block layer 160 in dummy device region 100 c indicates that asemiconductor material having a higher thermal conductivity than thesemiconductor material providing channel regions 112 of FinFETs 140 a inactive device region 100 a is utilized as a channel material for dummyFinFETs 140 c in dummy device region 100 c. Dummy FinFETs 140 c areusable as heat sinks to facilitate heat dissipation to the underlyingsubstrate.

Layout 600 is able to dissipate generated heat out of the structure byway of underlying substrate, source contact structures 172 andinterconnect metal layers 180.

One of ordinary skill would understand that any of the featuresdiscussed above with respect to FIGS. 2-5 including epitaxial blocklayer (FIG. 2 ), greater channel length (FIG. 3 ), greater gate pitch(FIG. 4 ) and NT_N layer (FIG. 5 ) are capable of being used to dummyFinFETs 140 c in dummy device region 100 c to maximize heat dissipation.

FIG. 7 is a schematic diagram of an analog circuit 700, in accordancewith some embodiments. Referring to FIG. 7 , analog circuit 700 includestransistors M1, M2 and M3, and resistors R1, R2, R3 and R4.

Transistors M1 and M2 each have source terminals electrically coupled toone another at node A. A drain terminal of transistor M1 is electricallycoupled to a first terminal of resistor R1, and a drain terminal oftransistor M2 is electrically coupled to a first terminal of resistorR2. A second terminal of resistor R1 and a second terminal of R2 areelectrically coupled to a supply voltage Vdd. A drain terminal oftransistor M3 is electrically coupled to node A, and a source terminalof transistor M3 is coupled to ground. Resistors R3 and R4 each have afirst terminal coupled to node N, and a second terminal being floating.Resistors R3 and R4 are configured to be located in close proximity totransistors M1 and M2, respectively. Because the second terminals ofrespective resistor R3 and R4 are floating and no current flows throughresistor R3 or R4, resistors R3 and R4 are usable to dissipate heatgenerated by respective transistors M1 and M2.

FIG. 8A is a plan view of a layout 800 of an analog circuit, inaccordance with some embodiments.

Referring to FIG. 8A, layout 800 includes at least one semiconductor fin810 and a plurality of gate structures 830 in an active device region800 a. Gate structures 830 cross semiconductor fin 810, thereby defininga plurality of FinFETs 840 in active device region 800 a. Each FinFET840 includes a gate structure 830 across a channel region 812 ofsemiconductor fin 810, and a source region 814 and a drain region 816 onopposite sides of the gate structure 830 surrounding channel region 812.

Layout 800 further includes a first resistor 820 a in a first passivedevice region 800 b adjacent to a first side of active device region 800a, and a second resistor 820 b in a second passive device region 800 cadjacent to a second side of active device region 800 a. Active deviceregion 800 a, first passive device region 800 b and second passivedevice region 800 c are separated from one another by isolationstructures 804. First passive device region 800 b is separated fromactive device region 800 a by a first spacing S1, and second passivedevice region 800 c is separated from active device region 800 a by asecond spacing S2. A minimum spacing allowed by design rules for spacingS1, S2 is desirable to maximize heat dissipation rate. Each resistor 820a, 820 b includes a doped well 822, and a first heavily doped region 824and a second heavily doped region 826 in doped well 822.

Layout 800 further includes a plurality of source contact structures 872and a plurality of drain contact structures 874. Each source contactstructure 872 overlies a corresponding source region 814 to provideelectrical connection to the corresponding source region 814. Each draincontact structure 874 overlies a corresponding drain region 816 toprovide electrical connection to the corresponding drain region 816.

Layout 800 further includes a plurality of source vias 882 contactingrespective source contact structures 872, a plurality of drain vias 884contacting respective drain contact structures 874, and a plurality ofresistor vias 886 contacting first heavily doped regions 824 ofrespective resistors 820 a, 820 b.

Layout 800 further includes a first interconnect metal layer 892 oversource vias 882 and resistor vias 886. First interconnect metal layer892 couples source regions 814 to first heavily doped regions 824 ofrespective resistors 820 a, 820 b by way of source contact structures872, source vias 882 and resistor vias 886. Heat generated by FinFETs840 thus is able to be dissipated from source regions 814 of FinFETs 840to resistors 820 a through first interconnect metal layer 892. Secondheavily doped regions 826 of respective resistors 820 a, 820 b are leftfloating, so that no current flows through respective resistors 820 a,820 b. The resistors 820 a, 820 b thus function as heat sinks to allowheat generated by FinFETs 840 in active device region 800 a to resistors820 a, 820 b.

Layout 800 further includes a second interconnect metal layer 894 overdrain vias 884. Second interconnect metal layer 894 couples drainregions 816 of FinFETs 840 together.

FIG. 8B is a cross-section view of a semiconductor device 800′manufactured according to the layout 800 depicted in FIG. 8A and takenalong line B-B′ in FIG. 8A. Semiconductor device 800′ is a non-limitedexample for facilitating the illustration of the present disclosure.

Semiconductor device 800′ includes a substrate 102 such as a siliconsubstrate. In some embodiments, substrate 802 is doped with p-typedopants such as boron. In other embodiments, substrate 802 is doped withn-type dopants such as phosphorous or arsenic.

Semiconductor device 800′ includes a plurality of FinFETs 840 formed inactive device region 800 a of substrate 802. In some embodiments,FinFETs 840 are configured as pFinFETs. In some embodiments, FinFETs 840are configured as nFinFETs. Each FinFET 840 includes a channel region812, a source region 814 on a first side of channel region 812, a drainregion 816 on a second side of channel region 812, and a gate structure830 over channel region 812. Each gate structure 830 includes a gatedielectric layer 832 and a gate electrode layer 834. FinFETs 840 aresubstantially identical in configuration to FinFETs 140 a describedabove in FIGS. 1B-1C and FIGS. 2B-2C. Materials described above tovarious components of FinFETs 140 a in FIGS. 1B and 1C are applicable tocorresponding components of FinFETs 840.

Each FinFET 840 is formed over an SRB layer 818. In some embodiments,SRB layer 818 includes SiGe configured to provide a stress to theoverlying channel region 812.

Semiconductor device 800′ further includes a first resistor 820 a formedin a first passive device region 800 b of substrate 802 and a secondresistor 820 b formed in a second passive device region 800 c (FIG. 8A).In some embodiments, each resistor 820 a, 820 b is configured as ann-well resistor. In some embodiments, each resistor 820 a, 820 b isconfigured as a p-well resistor. Each resistor 820 a, 820 b includes adoped well 822 and heavily doped regions 824, 826 formed in substrate802. Respective passive device regions 800 b, 800 c are separated fromactive device region 800 a by isolation structures 804. In someembodiments, isolation structures 804 include a dielectric materialdescribed above with respect to isolation structures 104.

Doped wells 822 are formed in substrate 802. In some embodiments, eachdoped well 822 is doped with dopants having an opposite doping polaritythan substrate 102. In some embodiments, each doped well 822 is ann-well for formation of an n-well resistor. In some embodiments, eachdoped well 822 is a p-well for formation of a p-well resistor. Heavilydoped regions 824, 826 are formed at the upper surface of each dopedwell 822 and adjoined to isolation structures 804. Heavily doped regions824, 826 have the same doping polarity as doped wells 822, but with ahigher doping concentration.

Semiconductor device 800′ further includes source contact structures 872over respective source regions 814 and drain contact structures 874 overrespective drain regions 816. In some embodiments, source contactstructures 872 and drain contact structures 874 include cobalt, copperor tungsten.

Semiconductor device 800′ further includes source vias 882 overrespective source contact structures, 872, drain vias 884 (FIG. 8A) overrespective drain contact structures 874, and resistor vias 886 overrespective heavily doped regions 824. A first interconnect metal layer892 is over source vias 882 and resistor vias 886 to couple sourceregions 814 of respective FinFETs 840 to heavily doped region 824 ofeach resistor 820 a, 820 b. A second interconnect metal layer 894 isover drain vias to couple drain regions 816 of respective FinFETs 840.Heavily doped region 826 of each resistor 820 a, 820 b is left floating.Vias 882, 884, 886 and interconnect metal layers 892, 894 include ametal such as aluminum, copper, tungsten, or alloys thereof.

The dashed arrows in FIG. 8B show the heat dissipation paths insemiconductor device 800′. Because no current is flow through respectiveresistors 820 a, 820 b, resistors 820 a, 820 b that are in closeproximity of FinFETs 840 function as heat sinks to remove a majority ofheat generated by FinFETs 840 to passive device regions 880 b, 800 c ofsubstrate 802 as indicated by arrow 895. In addition, some of heatgenerated by FinFETs 840 is able to be dissipated from source regions814 of FinFETs 840 to resistors 820 a, 820 b by way of source contactstructures 872, source vias 882, first interconnect metal layer 892 andresistor vias 886 as indicated by arrow 897.

While specific examples of n- or p-well resistors are described, othertypes of resistors such as, for example, polysilicon resistors, TiNresistors, metal resistors, or OD (active area) resistors arecontemplated and within the scope of the present disclosure.

FIG. 9 is a schematic diagram of an electronic design automation (EDA)system 900, in accordance with some embodiments. Methods describedherein of generating design layouts, e.g., layouts 100, 200, 300, 400,500, 600 and 800, in accordance with one or more embodiments, areimplementable, for example, using EDA system 900, in accordance withsome embodiments. In some embodiments, EDA system 900 is a generalpurpose computing device including a hardware processor 902 and anon-transitory, computer-readable storage medium 904. Computer-readablestorage medium 904, amongst other things, is encoded with, i.e., stores,a set of executable instructions 906, design layouts 907, design rulecheck (DRC) decks 909 or any intermediate data for executing the set ofinstructions. Each design layout 907 comprises a graphicalrepresentation of an integrated chip, such as for example, a GSII file.Each DRC deck 909 comprises a list of design rules specific to asemiconductor process chosen for fabrication of a design layout 907.Execution of instructions 906, design layouts 907 and DRC decks 909 byhardware processor 902 represents (at least in part) an EDA tool whichimplements a portion or all of, e.g., the methods described herein inaccordance with one or more (hereinafter, the noted processes and/ormethods).

Processor 902 is electrically coupled to computer-readable storagemedium 904 via a bus 908. Processor 902 is also electrically coupled toan I/O interface 910 by bus 908. A network interface 912 is alsoelectrically connected to processor 902 via bus 908. Network interface912 is connected to a network 914, so that processor 902 andcomputer-readable storage medium 904 are capable of connecting toexternal elements via network 914. Processor 902 is configured toexecute instructions 906 encoded in computer-readable storage medium 904in order to cause EDA system 900 to be usable for performing a portionor all of the noted processes and/or methods. In one or moreembodiments, processor 902 is a central processing unit (CPU), amulti-processor, a distributed processing system, an applicationspecific integrated circuit (ASIC), and/or a suitable processing unit.

In one or more embodiments, computer-readable storage medium 904 is anelectronic, magnetic, optical, electromagnetic, infrared, and/or asemiconductor system (or apparatus or device). For example,computer-readable storage medium 904 includes a semiconductor orsolid-state memory, a magnetic tape, a removable computer diskette, arandom access memory (RAM), a read-only memory (ROM), a rigid magneticdisk, and/or an optical disk. In one or more embodiments using opticaldisks, computer-readable storage medium 904 includes a compact disk-readonly memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or adigital video disc (DVD).

In one or more embodiments, computer-readable storage medium 904 storesinstructions 906, design layouts 907 and DRC decks 909 configured tocause EDA system 900 (where such execution represents (at least in part)the EDA tool) to be usable for performing a portion or all of the notedprocesses and/or methods. In one or more embodiments, storage medium 904also stores information which facilitates performing a portion or all ofthe noted processes and/or methods.

EDA system 900 includes I/O interface 910. I/O interface 910 is coupledto external circuitry. In one or more embodiments, I/O interface 910includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen,and/or cursor direction keys for communicating information and commandsto processor 902.

EDA system 900 also includes network interface 912 coupled to processor902. Network interface 912 allows EDA system 900 to communicate withnetwork 914, to which one or more other computer systems are connected.Network interface 912 includes wireless network interfaces such asBLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces suchas ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion orall of noted processes and/or methods, is implemented in two or more EDAsystems 900.

EDA system 900 is configured to receive information through I/Ointerface 910. The information received through I/O interface 910includes one or more of instructions, data, design rules, libraries ofstandard cells, and/or other parameters for processing by processor 902.The information is transferred to processor 902 via bus 908. EDA system900 is configured to receive information related to a user interface(UI) 942 through I/O interface 910. The information is stored incomputer-readable medium 904 as UI 942.

In some embodiments, a layout diagram which includes standard cells isgenerated using a tool such as VIRTUOSO® available from CADENCE DESIGNSYSTEMS, Inc., or another suitable layout generating tool.

In some embodiments, the processes are realized as functions of aprogram stored in a non-transitory computer readable recording medium.Examples of a non-transitory computer readable recording medium include,but are not limited to, external/removable and/or internal/built-instorage or memory unit, e.g., one or more of an optical disk, such as aDVD, a magnetic disk, such as a hard disk, a semiconductor memory, suchas a ROM, a RAM, a memory card, and the like.

FIG. 10 is a block diagram of a semiconductor device manufacturingsystem 1000, and a device manufacturing flow associated therewith, inaccordance with some embodiments. In some embodiments, based on designlayout, e.g., layout 100, 200, 300, 400, 500, 600, 800, at least one ofone or more semiconductor masks or at least one component in a layer ofa semiconductor integrated circuit is fabricated using semiconductordevice manufacturing system 1000.

In FIG. 10 , semiconductor device manufacturing system 1000 includesentities, such as a design house 1020, a mask house 1030, and asemiconductor device manufacturer/fabricator (“fab”) 1050, that interactwith one another in the design, development, and manufacturing cyclesand/or services related to manufacturing semiconductor device 1060. Theentities in semiconductor device manufacturing system 1000 are connectedby a communications network. In some embodiments, the communicationsnetwork is a single network. In some embodiments, the communicationsnetwork is a variety of different networks, such as an intranet and theInternet. The communications network includes wired and/or wirelesscommunication channels. Each entity interacts with one or more of theother entities and provides services to and/or receives services fromone or more of the other entities. In some embodiments, two or more ofdesign house 1020, mask house 1030, and fab 1050 is owned by a singlelarger company. In some embodiments, two or more of design house 1020,mask house 1030, and fab 1050 coexist in a common facility and usecommon resources.

Design house (or design team) 1020 generates a design layout 1022.Design layout 1022 includes various geometrical patterns designed for asemiconductor device 1060. The geometrical patterns correspond topatterns of metal, oxide, or semiconductor layers that make up thevarious components of semiconductor device 1060 to be fabricated. Thevarious layers combine to form various device features. For example, aportion of design layout 1022 includes various circuit features, such asan active region, gate structures, source contact structures and draincontact structures, and metal lines or vias of interconnection, to beformed in a semiconductor substrate (such as a silicon wafer) andvarious material layers disposed on the semiconductor substrate. Designhouse 1020 implements a proper design procedure to form design layout1022. The design procedure includes one or more of logic design,physical design or place and route. Design layout 1022 is presented inone or more data files having information of the geometrical patterns.For example, design layout 1022 can be expressed in a GDSII file formator DFII file format.

Mask house 1030 includes mask data preparation 1032 and mask fabrication1044. Mask house 1030 uses design layout 1022 to manufacture one or moremasks 1045 to be used for fabricating the various layers ofsemiconductor device 1060 according to design layout 1022. Mask house1030 performs mask data preparation 1032, where design layout 1022 istranslated into a representative data file (“RDF”). Mask datapreparation 1032 provides the RDF to mask fabrication 1044. Maskfabrication 1044 includes a mask writer. A mask writer converts the RDFto an image on a substrate, such as a mask (reticle) 1045 or asemiconductor wafer 1053. Design layout 1022 is manipulated by mask datapreparation 1032 to comply with particular characteristics of the maskwriter and/or requirements of fab 1050. In FIG. 10 , mask datapreparation 1032 and mask fabrication 1044 are illustrated as separateelements. In some embodiments, mask data preparation 1032 and maskfabrication 1044 can be collectively referred to as mask datapreparation.

In some embodiments, mask data preparation 1032 includes opticalproximity correction (OPC) which uses lithography enhancement techniquesto compensate for image errors, such as those that can arise fromdiffraction, interference, other process effects and the like. OPCadjusts design layout 1022. In some embodiments, mask data preparation1032 includes further resolution enhancement techniques (RET), such asoff-axis illumination, sub-resolution assist features, phase-shiftingmasks, other suitable techniques, and the like or combinations thereof.In some embodiments, inverse lithography technology (ILT) is also used,which treats OPC as an inverse imaging problem.

In some embodiments, mask data preparation 1032 includes a mask rulechecker (MRC) that checks design layout 1022 that has undergoneprocesses in OPC with a set of mask creation rules which contain certaingeometric and/or connectivity restrictions to ensure sufficient margins,to account for variability in semiconductor manufacturing processes, andthe like. In some embodiments, the MRC modifies design layout 1022 tocompensate for limitations during mask fabrication 1044, which may undopart of the modifications performed by OPC in order to meet maskcreation rules.

In some embodiments, mask data preparation 1032 includes lithographyprocess checking (LPC) that simulates processing that will beimplemented by fab 1050 to fabricate semiconductor device 1060. LPCsimulates this processing based on design layout 1022 to create asimulated manufactured device, such as semiconductor device 1060. Theprocessing parameters in LPC simulation can include parametersassociated with various processes of the IC manufacturing cycle,parameters associated with tools used for manufacturing the IC, and/orother aspects of the manufacturing process. LPC takes into accountvarious factors, such as aerial image contrast, depth of focus (“DOF”),mask error enhancement factor (“MEEF”), other suitable factors, and thelike or combinations thereof. In some embodiments, after a simulatedmanufactured device has been created by LPC, if the simulated device isnot close enough in shape to satisfy design rules, OPC and/or MRC are berepeated to further refine design layout 1022.

One of ordinary skill would understand that the above description ofmask data preparation 1032 has been simplified for the purposes ofclarity. In some embodiments, mask data preparation 1032 includesadditional features such as a logic operation (LOP) to modify designlayout 1022 according to manufacturing rules. Additionally, theprocesses applied to design layout 1022 during mask data preparation1032 may be executed in a variety of different orders.

After mask data preparation 1032 and during mask fabrication 1044, amask 1045 or a group of masks 1045 are fabricated based on design layout1022. In some embodiments, mask fabrication 1044 includes performing oneor more lithographic exposures based on design layout 1022. In someembodiments, an electron-beam (e-beam) or a mechanism of multiplee-beams is used to form a pattern on a mask (e.g., a photomask, or areticle) 1045 based on design layout 1022. Mask 1045 can be formed invarious technologies. In some embodiments, mask 1045 is formed usingbinary technology. In some embodiments, a mask pattern includes opaqueregions and transparent regions. A radiation beam, such as anultraviolet (UV) beam, used to expose the image sensitive material layer(e.g., photoresist) which has been coated on a wafer, is blocked by theopaque regions and transmits through the transparent regions. In oneexample, a binary mask version of mask 1045 includes a transparentsubstrate (e.g., fused quartz) and an opaque material (e.g., chromium)coated in the opaque regions of the binary mask. In another example,mask 1045 is formed using a phase shift technology. In a phase shiftmask (PSM) version of mask 1045, various features in the pattern formedon the phase shift mask are configured to have proper phase differenceto enhance the resolution and imaging quality. In various examples, thephase shift mask can be attenuated PSM or alternating PSM. The mask(s)generated by mask fabrication 1044 is used in a variety of processes.For example, such a mask(s) is used in an ion implantation process toform various doped regions in semiconductor wafer 1053, in an etchingprocess to form various etching regions in semiconductor wafer 1053,and/or in other suitable processes.

Fab 1050 includes wafer fabrication 1052. Fab 1050 is an IC fabricationbusiness that includes one or more manufacturing facilities for thefabrication of a variety of different IC products. In some embodiments,fab 1050 is a semiconductor foundry. For example, there may be amanufacturing facility for the front end fabrication of a plurality ofIC products (front-end-of-line (FEOL) fabrication), while a secondmanufacturing facility may provide the back end fabrication for theinterconnection and packaging of the IC products (BEOL fabrication), anda third manufacturing facility may provide other services for thefoundry business.

Fab 1050 uses mask(s) 1045 fabricated by mask house 1030 to fabricatesemiconductor device 1060. Thus, fab 1050 at least indirectly usesdesign layout 1022 to fabricate semiconductor device 1060. In someembodiments, semiconductor wafer 1053 is fabricated by fab 1050 usingmask(s) 1045 to form semiconductor device 1060. In some embodiments, thedevice fabrication includes performing one or more lithographicexposures based at least indirectly on design layout 1022. Semiconductorwafer 1053 includes a silicon substrate or other proper substrate havingmaterial layers formed thereon. Semiconductor wafer 1053 furtherincludes one or more of various doped regions, dielectric features,multilevel interconnects, and the like (formed at subsequentmanufacturing steps).

Details regarding an integrated circuit (IC) manufacturing system (e.g.,semiconductor device manufacturing system 1000 of FIG. 10 ), and an ICmanufacturing flow associated therewith are found, e.g., in U.S. Pat.No. 9,256,709, granted Feb. 9, 2016, U.S. Pre-Grant Publication No.20150278429, published Oct. 1, 2015, U.S. Pre-Grant Publication No.20140040838, published Feb. 6, 2014, and U.S. Pat. No. 7,260,442,granted Aug. 21, 2007, the entireties of each of which are herebyincorporated by reference.

An aspect of this description relates to a method of making asemiconductor device. The method includes forming an active deviceregion in a substrate. The method further includes forming a firsttransistor in the active device region, the first transistor including afirst channel region a first source region and a first drain region. Themethod further includes forming a guard ring region outside the activedevice region. The method further includes forming a second transistorin the guard ring region, the second transistor comprising a secondchannel region a second source region and a second drain region. Thesecond channel region includes a semiconductor material having a higherthermal conductivity than a semiconductor material of the first channelregion. In some embodiments, the method further includes electricallyconnecting the first source region to the second source region. In someembodiments, forming the first transistor includes forming a fin fieldeffect transistor (FinFET). In some embodiments, the method furtherincludes forming a source contact structure over the first source regionand the second source region. In some embodiments, forming the sourcecontact structure includes forming the source contact structure as acontinuous layer. In some embodiments, the method further includesforming a first gate structure over the first channel region. In someembodiments, the method further includes forming a second gate structureover the second channel region. In some embodiments, forming the secondtransistor includes forming the second transistor spaced from the firsttransistor in a first direction parallel to a top surface of thesubstrate. In some embodiments, forming the second transistor includesforming the second source region offset from the first source region ina second direction, and the second direction is perpendicular to thefirst direction. In some embodiments, forming the second transistorincludes forming the second source region aligned with the first channelregion in the first direction.

An aspect of this description relates to a method of forming asemiconductor device. The method includes forming a first transistor inan active device region, wherein the first transistor includes a firstchannel region. The method further includes forming a second transistorin a guard ring region, wherein the second transistor includes a secondchannel region, and a thermal conductivity of the second channel regionis greater than a thermal conductivity of the first channel region. Insome embodiments, forming the first transistor includes doping the firstchannel region to have a first dopant concentration, and forming thesecond transistor includes doping the second channel region to have asecond dopant concentration less than the first dopant concentration. Insome embodiments, forming the first transistor includes forming thefirst channel region including SiGe. In some embodiments, forming thesecond transistor includes forming the second channel region includingSi. In some embodiments, forming the second transistor includes formingan inactive device.

An aspect of this description relates to a method of making asemiconductor device. The method includes forming an active deviceregion in a substrate. The method further includes forming a transistorin the active device region, the transistor including a channel regionand a source/drain (S/D) region. The method further includes defining apassive device region in the substrate. The method further includesforming a resistor in the passive device region. The method furtherincludes forming a contact structure overlying the S/D region. Themethod further includes forming an interconnect layer electricallycoupling the contact structure and a first terminal of the resistor,wherein a second terminal of the resistor is floating. In someembodiments, forming the resistor includes forming a doped well in thepassive device region; and forming a highly doped well in the dopedwell. In some embodiments, forming the interconnect layer includeselectrically connecting the contact structure to the highly doped well.In some embodiments, forming the resistor includes forming the resistoron an opposite side of the S/D region from the channel region. In someembodiments, the method further includes forming a second resistor on anopposite side of the transistor from the resistor; and electricallyconnecting the S/D region to the second resistor.

It will be readily seen by one of ordinary skill in the art that thedisclosed embodiments fulfill one or more of the advantages set forthabove. After reading the foregoing specification, one of ordinary skillwill be able to affect various changes, substitutions of equivalents andvarious other embodiments as broadly disclosed herein. Although featuresof various embodiments are expressed in certain combinations among theclaims, it is contemplated that these features can be arranged in anycombination and order. It is therefore intended that the protectiongranted hereon be limited only by the definition contained in theappended claims and equivalents thereof.

What is claimed is:
 1. A method of making a semiconductor device, themethod comprising: forming an active device region in a substrate;forming a first transistor in the active device region, the firsttransistor comprising a first channel region a first source region and afirst drain region; and forming a guard ring region outside the activedevice region; forming a second transistor in the guard ring region, thesecond transistor comprising a second channel region a second sourceregion and a second drain region, wherein the second channel regioncomprises a semiconductor material having a higher thermal conductivitythan a semiconductor material of the first channel region.
 2. The methodof claim 1, further comprises electrically connecting the first sourceregion to the second source region.
 3. The method of claim 1, whereinforming the first transistor comprises forming a fin field effecttransistor (FinFET).
 4. The method of claim 1, further comprisingforming a source contact structure over the first source region and thesecond source region.
 5. The method of claim 4, wherein forming thesource contact structure comprises forming the source contact structureas a continuous layer.
 6. The method of claim 1, further comprisingforming a first gate structure over the first channel region.
 7. Themethod of claim 6, further comprising forming a second gate structureover the second channel region.
 8. The method of claim 1, whereinforming the second transistor comprises forming the second transistorspaced from the first transistor in a first direction parallel to a topsurface of the substrate.
 9. The method of claim 8, wherein forming thesecond transistor comprises forming the second source region offset fromthe first source region in a second direction, and the second directionis perpendicular to the first direction.
 10. The method of claim 8,wherein forming the second transistor comprises forming the secondsource region aligned with the first channel region in the firstdirection.
 11. A method of forming a semiconductor device, the methodcomprising: forming a first transistor in an active device region,wherein the first transistor comprises a first channel region, forming asecond transistor in a guard ring region, wherein the second transistorcomprises a second channel region, and a thermal conductivity of thesecond channel region is greater than a thermal conductivity of thefirst channel region.
 12. The method of claim 11, wherein forming thefirst transistor comprises doping the first channel region to have afirst dopant concentration, and forming the second transistor comprisesdoping the second channel region to have a second dopant concentrationless than the first dopant concentration.
 13. The method of claim 11,wherein forming the first transistor comprises forming the first channelregion comprising SiGe.
 14. The method of claim 13, wherein forming thesecond transistor comprises forming the second channel region comprisingSi.
 15. The method of claim 11, wherein forming the second transistorcomprises forming an inactive device.
 16. A method of making asemiconductor device, the method comprising: forming an active deviceregion in a substrate; forming a transistor in the active device region,the transistor comprising a channel region and a source/drain (S/D)region; defining a passive device region in the substrate; forming aresistor in the passive device region; forming a contact structureoverlying the S/D region; and forming an interconnect layer electricallycoupling the contact structure and a first terminal of the resistor,wherein a second terminal of the resistor is floating.
 17. The method ofclaim 16, wherein forming the resistor comprises: forming a doped wellin the passive device region; and forming a highly doped well in thedoped well.
 18. The method of claim 17, wherein forming the interconnectlayer comprises electrically connecting the contact structure to thehighly doped well.
 19. The method of claim 16, wherein forming theresistor comprises forming the resistor on an opposite side of the S/Dregion from the channel region.
 20. The method of claim 16, furthercomprising: forming a second resistor on an opposite side of thetransistor from the resistor; and electrically connecting the S/D regionto the second resistor.